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High CMRR Instrumentation Amplifier (Schematic and Layout) design for biomedical applications

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Instrumentation amplifiers are intended to be used whenever acquisition of a useful signal is difficult. IA’s must have extremely high input impedances because source impedances may be high and/or unbalanced. bias and offset currents are low and relatively stable so that the source impedance need not be constant. Balanced differential inputs are provided so that the signal source may be referenced to any reasonable level independent of the IA output load reference. Common mode rejection, a measure of input balance, is very high so that noise pickup and ground drops, characteristic of remote sensor applications, are minimized.Care is taken to provide high, well characterized stability of critical parameters under varying conditions, such as changing temperatures and supply voltages. Finally, all components that are critical to the performance of the IA are internal to the device. The precision of an IA is provided at the expense of flexibility. By committing to the one specific task of
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Setup and hold – the device perspective

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In our previous post, Setup and hold – the state machine perspective, we discussed how setup and hold can be defined in respect of state machines. Interestingly, there is another perspective of setup and hold – that in repect to devices, known as setup and hold time requirements. For a device, (for example a flip-flop, a latch or an SoC), setup and hold times are defined as:
Setup time: Setup time of a device is defined as the minimum time before the clock edge the data should be kept stable so that it is reliably sampled by the clock.
Hold time: Hold time of a device is defined as the minimum time after the clock edge the data should be kept stable so that it is reliably sampled by the clock.

In other words, every device has a setup and hold window surrounding the active clock edge within which data should be kept stable. As is shown in figure 1, brown line represents the active clock edge, blue line represents setup window and red line represents hold window. As is shown, data can toggle at any time except between setup and hold windows. Toggling of data between setup-hold window means flip-flop might go into metastable state and the output of flip-flop does not remain predictable.
Setup check for data path being launched from positive edge-triggered flip-flop is single cycle and hold check is zero cycle
Figure 1: Setup and hold checks
Origin of setup and hold timing requirements: Let us consider a positive edge-triggered flip-flop. Figure 2 shows a most simplistic circuit for a practical flip-flop. Inverters I1, I2 and Transmission gates G1, G2 constitute master latch and I3, I4, G3, G4 constitute slave latch.
A positive edge-triggered flip-flop consists of master and slave latches, each of which consists of two inverters connected in positive loop back mode and two transmission gates
Figure 2: A typical practical circuit for negative edge-triggered flip-flop
Figure 3 below shows the origin of setup time requirement. For data to get latched properly, it should complete the feedback loop of master latch before the closing edge of clock at transmission gate G4. So, setup time requirement of the flip-flop is:
Tsetup = TG3 + TI1 + TI2 + TG4
The setup check of a flip-flop consists of delay of input transmission gate and feedback transmission gate and the two inverters of master latch
Figure 3: Figure demonstrating delays constituting setup check
Similarly, figure 4 below shows the origin of hold timing requirement. For data to get latched properly, the next data should not cross inverter I1. So, hold timing requirement of the flip-flop is:
Thold = TG3 + TI1

In other words, hold time is the minimum time required for the data to change after the clock edge has passed so that new data does not get captured at the present clock edge.
Hold check consists of input transmission gate delay and input inverter delay of master latch in flip-flop
Figure 4: Delays constituted in hold check


Thus, in this post, we have discussed the origin of setup and hold checks for a device.

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