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High CMRR Instrumentation Amplifier (Schematic and Layout) design for biomedical applications

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Instrumentation amplifiers are intended to be used whenever acquisition of a useful signal is difficult. IA’s must have extremely high input impedances because source impedances may be high and/or unbalanced. bias and offset currents are low and relatively stable so that the source impedance need not be constant. Balanced differential inputs are provided so that the signal source may be referenced to any reasonable level independent of the IA output load reference. Common mode rejection, a measure of input balance, is very high so that noise pickup and ground drops, characteristic of remote sensor applications, are minimized.Care is taken to provide high, well characterized stability of critical parameters under varying conditions, such as changing temperatures and supply voltages. Finally, all components that are critical to the performance of the IA are internal to the device. The precision of an IA is provided at the expense of flexibility. By committing to the one specific task of
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How delay of a standard cell changes with drive strength

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A standard cell (let us say a buffer) can be represented as shown in figure 1 below, where 
R = Channel resistance 
Cds = Drain-to-source capacitance (internal capacitance of cell)
Cload = Load capacitance


So, RC time constant can be represented as "R * (Cds + Cload)".

What happens on increasing the drive strength? In our post "what is meant by drive strength", we discussed that the drive strength of a standard cell increases when we increase the size of its transistors. So, basically, a cell with drive strength 2X will have twice of width as compared to the one with 1X drive strength.
And we know that
Channel resistance decreases with "W".
Drain-to-source capacitance increases with "W".
So,  upon increasing the drive strength, its internal capacitance will increase and channel resistance will reduce by same amount. The same is depicted in figure 2 below.


Time constant of "1X" buffer = R * (Cds + Cload)
 Time constant of "2X" buffer = R/2 * (2Cds + Cload) 
Now, let us talk of following scenarios:

Special case 1: Load capacitance is negligible.
In this scenario, we are left with only internal resistance and capacitance of the cell.

Time constant of "1X" buffer = R * Cds
Time constant of "2X" buffer = R * Cds
So, in this case, there should not be any impact of increasing the drive strength of standard cell on delay. So, in case there is negligible load, we should not upsize the standard cell. Doing so may instead increase the overall path delay as increased drive strength cell will present increased load to the previous stage cell, thereby increasing the delay of previous stage.

Special case 2: Load capacitance is very large as compared to internal capacitance.
In this scenario,
Time constant of "1X" buffer = R * Cload
Time constant of "2X" buffer = (R * Cload ) / 2 
So, second buffer will take approximately half the time to charge the load capacitance as compared to "1X" buffer.

So, we see that the the maximum possible benefit in delay by increasing the drive strength of standard cell is a reduction by a factor of two. In the worst case, we may not see any benefit at all.

We can also look at above equation by splitting cell delay into two components:
  1. Cell delay due to its own intrinsic capacitance: It does not scale by drive strength and is a constant value for one kind of standard cells.
  2. Cell delay due to external load capacitance: It is variable and decreases as we increase the drive strength of standard cell.

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