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High CMRR Instrumentation Amplifier (Schematic and Layout) design for biomedical applications

Instrumentation amplifiers are intended to be used whenever acquisition of a useful signal is difficult. IA’s must have extremely high input impedances because source impedances may be high and/or unbalanced. bias and offset currents are low and relatively stable so that the source impedance need not be constant. Balanced differential inputs are provided so that the signal source may be referenced to any reasonable level independent of the IA output load reference. Common mode rejection, a measure of input balance, is very high so that noise pickup and ground drops, characteristic of remote sensor applications, are minimized.Care is taken to provide high, well characterized stability of critical parameters under varying conditions, such as changing temperatures and supply voltages. Finally, all components that are critical to the performance of the IA are internal to the device. The precision of an IA is provided at the expense of flexibility. By committing to the one specific task of

Duty cycle variation of inter-clock timing paths

In the post, duty cycle variation, we understood what duty cycle variation is, and how to apply for intra-clock timing paths. But of similar importance is duty cycle variation as applied to inter-clock timing paths. Let us discuss these cases one-by-one:

Root clock to root-inverted clock: Inverted clock is same as root clock in frequency, with phase inverted. So, duty cycle variation needs to be applied for following cases:

  • Root rise edge -> generated rise edge
  • Root fall edge -> generated fall edge
  • Generated rise edge -> Root rise edge
  • Generated fall edge -> Root fall edge

Following commands will be needed to be applied:
set_clock_uncertainty -rise_from root_clk -rise_to gen_clk <duty_cycle> 
set_clock_uncertainty -fall_from root_clk -fall_to gen_clk <duty_cycle>
set_clock_uncertainty -rise_from gen_clk -rise_to root_clk <duty_cycle>
set_clock_uncertainty -fall_from gen_clk -fall_to root_clk <duty_cycle>

Root clock to odd 50% divided clock: In this scenario, we need to apply extra uncertainty for the following cases:

  • Root rise edge -> Generated fall edge
  • Root fall edge -> Generated rise edge
  • Generated rise edge -> Root fall edge
  • Generated fall edge -> Root rise edge


Following commands will need to be applied for this case:
set_clock_uncertainty -rise_from root_clk -fall_to gen_clk <duty cycle>
set_clock_uncertainty -fall_from root_clk -rise_to gen_clk <duty cycle>
set_clock_uncertainty -rise_from gen_clk -fall_to root_clk <duty cycle>
set_clock_uncertainty -fall_from gen_clk -rise_to root_clk <duty cycle>

Root clock to even 50% divided clock: In this case, we need to apply duty cycle uncertainty for the following cases:

  • Root fall edge -> Generated rise edge
  • Root fall edge -> Generated fall edge
  • Generated rise edge -> Root fall edge
  • Generated fall edge -> Root fall edge
Below figure shows these cases for a 50% divided clock from root clock.


 

So, the rule of thumb is same. Wherever there is a timing path wherein both rising and falling edges of root clock are involved, duty cycle variation will come into play. If you just keep this basic thing into mind, duty cycle variation will never haunt you. :-)

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