Build a Stabilized Capacitance Buffer Circuit Diagram

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This is a simplest Stabilized Capacitance Buffer Circuit Diagram. In this simple circuit using Ql and Q2 constitute a simple, high-speed FET input buffer. Ql functions as a source follower, with the Q2 current source load setting the drain-source channel current. The LT1010 buffer provides output drive capability for cables or whatever load is required. Normally, this open-loop configuration would be quite drifty because there is no de feedback. 

Stabilized Capacitance Buffer Circuit Diagram

Build a Stabilized Capacitance Buffer Circuit Diagram


The LTC1052 contributes this function to stabilize the circuit. It does this by comparing the filtered circuit output to a similarly filtered version of the input signal. The amplified difference between these signals is used to set Q2`s bias, and hence Ql `s channel current. Ql `s source line ensures that the gate never forward biases, and the 2000 pF capacitor at Al provides stable loop compensation. 

The rc network in Al`s output prevents it from seeing high-speed edges coupled through Q2`s collector-base junction. A2`s output is also fed back to the shield around Ql`s gate lead, bootstrapping the circuit`s effective in_put capacitance down to less than 1 pF.
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