tag:blogger.com,1999:blog-11380579776670104322024-03-14T10:35:52.974+05:30ElectronictheoryBy Bhupinder Singh and Harbinder Singh . GianParkash Inc.Anonymoushttp://www.blogger.com/profile/00616013923393611084noreply@blogger.comBlogger1105125tag:blogger.com,1999:blog-1138057977667010432.post-63933334322280690962018-09-23T07:20:00.000+05:302018-12-23T01:21:39.330+05:30DESIGN PROBLEM : 4-bit increment by 2 circuitProblem: Derive the logical expression for a 4-bit increment by 2 circuit and draw the architecture of it.Solution: The task here is to design a circuit that increments its count by two. Since, it is a 4-bit circuit, the total number of possible states is 16. Each state transitions to the state which has a binary value two greater than it. Now, there are two possible scenarios based upon the adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-43288613358581310722018-08-27T21:43:00.000+05:302018-12-23T01:21:39.689+05:30Clock gating checks in case of mux select transition when both clocks are runningPROBLEM: In the following figure, it is desired to toggle the select of the mux from CLOCK_DIV to CLOCK and both the clocks are running. What are the architectural and STA considerations for the same?SOLUTION:This is a very good example to understand how clock gating checks work, although you may/may not find any practical application for the same. We have to toggle the select of the multiplexer adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-64026196930326443052018-08-12T18:31:00.000+05:302018-12-23T01:21:40.047+05:30Intricacies in handling of half cycle timing pathsWhat is a half cycle path? A half cycle timing path is one in which launch and capture happen on different clock edges. A half cycle path can be in terms of both setup and hold. However, normally, in technical terms half cycle path is the one which has setup check getting formed as half cycle. For instance, following are some of the examples of half cycle timing paths:A timing path from positive adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-51123634419452375142018-07-23T20:30:00.000+05:302018-12-23T01:21:40.347+05:30Is hold always checked on the same edge?One of the guys asked me a question, "Why is hold always checked on the same edge?" Normally, it is taught in books/colleges that hold is frequency independent because it is checked on same edge. But, is it really true? It is true only for some of the many cases. Hold can be checked on the same edge, next edge or previous edge depending upon the scenario. In this post, we will discuss those casesadminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-86446872794916134212018-05-19T19:18:00.000+05:302018-12-23T01:21:40.645+05:30Design puzzle : 2-input mux glitch issueProblem statement: A 2-input multiplexer has both of its inputs getting value of "1". Will there be any toggle (glitch) happening at the output of the multiplexer? If yes, is that expected? What if both the inputs are getting value of "0"?Answer: We all know that a multiplexer's output is equal toIN0 if SEL = 0IN1 if SEL =1So, if both IN0 and IN1 are getting same logic value, output must notadminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-26797679312458027252018-01-15T06:04:00.000+05:302018-12-23T01:21:40.940+05:30Setup and hold – the device perspectiveIn our previous post, Setup and hold – the state machine perspective, we discussed how setup and hold can be defined in respect of state machines. Interestingly, there is another perspective of setup and hold – that in repect to devices, known as setup and hold time requirements. For a device, (for example a flip-flop, a latch or an SoC), setup and hold times are defined as:Setup time: Setup timeadminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-66461599473020510262017-12-29T08:38:00.000+05:302018-12-23T01:21:41.240+05:30Design problem: Clock gating for a shift registerProblem: There is an 4-bit shift register with parallel read and write capability as shown in the diagram. We need to find out an opportunity to clock gate the module. Mode selection bits ("S1" and "S0") are controlling the operation of this shift register with following settings:Solution: From the basics of clock gating, we know that if the stae of a flip-flop is not chaging, there lies an adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-30039839496968874962017-12-22T07:32:00.000+05:302018-12-23T01:21:41.536+05:30MOS transistor structureA MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or MOS, as is commonly called, is an electronic device which converts change in input voltage into a change in output current. The basic structure of a MOS transistor (as seen sideways) is as shown in figure 1. The substrate is a lightly doped semiconductor. Source and Drain regions are heavily doped regions of type opposite to adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-70964569372472960732017-12-15T20:51:00.000+05:302018-12-23T01:21:41.829+05:30What is the difference between a normal buffer and clock buffer?A buffer is an element which produces an output signal, which is of the same value as the input signal. We can also refer a buffer as a repeater which repeats the signal it is receiving, just as there are repeaters in telephone signal transmission lines. You must have noticed that we have two kinds of buffers (or any logic gate) available in standard cell libraries as:Clock buffer: The clock adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-27394564581258905002017-12-10T09:28:00.000+05:302018-12-23T01:21:42.136+05:30Performance gain with latchesThe property of latches being transparent gives them a basic characteristic, known as time borrowing, owing to which they can capture data over a period of time rather than an instant. Using this property of latches intelligently can result in performance advantage for specific design scenarios, especially for designs having asymmetric data paths in subsequent stages. Let us elaborate with the adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-17457204207967998442017-12-04T16:59:00.000+05:302018-12-23T01:21:42.433+05:30How delay of a standard cell changes with drive strengthA standard cell (let us say a buffer) can be represented as shown in figure 1 below, where R = Channel resistance Cds = Drain-to-source capacitance (internal capacitance of cell)Cload = Load capacitanceSo, RC time constant can be represented as "R * (Cds + Cload)".What happens on increasing the drive strength? In our post "what is meant by drive strength", we discussed that the adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-5994007014813384832017-11-27T08:30:00.000+05:302018-12-23T01:21:42.730+05:30What is meant by drive strength of a standard cellAs we know that cell delay is a function of output load capacitance. The most simplistic equivalent circuit of a logic gate driving an output can be assumed as given in figure 1:The purpose of logic gate is to propagate the effect of logic value available at its input to the output. Based upon whether '0' or '1' is to be propagated to the output. The corresponding is achieved by charging and adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-29008113108897725022017-11-21T08:34:00.000+05:302018-12-23T01:21:43.028+05:30Setup/hold – the state machines essentialsHi friends, in the post State machines – a practical perspective, we learnt about state machines. We also discussed different aspects of a state machine with the help of an example and the need of setup and hold checks to be taken care of. In this post, we will be discussing the state machine with a pinch of setup and hold and try to build a better understanding regarding these. For adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-60184615717455164012017-11-13T20:00:00.000+05:302018-12-23T01:21:43.322+05:30Design problem: How can you convert an XOR gate into a buffer or an inverter?Figure 1 above shows the truth table of a 2-input XOR gate. It has two inputs A, B and an output OUT. On looking closely, we observe that:If one of the inputs (say B) is 0, OUT is equal to the other input. For instance, when B = 0,OUT = 0 when A = 0OUT = 1 when A = 1Similarly, if one of the inputs is 1, OUT is equal to invert of the other input. For instance, when B = 1,OUT = 1 when A = 0OUT = 0 adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-36445150347393253102017-11-10T07:12:00.000+05:302018-12-23T01:21:43.618+05:30Minimum pulse width violation exampleSTA problem: Consider below figure, wherein minimum pulse width requirement of a flip-flop is 590 ps. It is getting clocked by a PLL of 500 MHz with a duty cycle variation of 60 ps. There are 30 buffers in clock path, each having a rise delay of 60 ps and fall delay of 48 ps. Will this setup be able to meet the duty cycle requirement of flip-flop? Find the slack available.Solution: Here, we must adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-37358025307705318512017-10-31T08:25:00.000+05:302018-12-23T01:21:43.912+05:30Glitches in combinational circuitsWhat is a glitch: As per definition, a glitch is any unwanted pulse at the output of a combinational gate. In other words, a glitch is a small spike that happens at the output of a gate. A glitch happens generally, if the delays to the combinational gate output are not balanced. For instance, consider an AND gate with one of its inputs getting inverted and delayed version of its other inputadminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-11588358375139108522017-10-23T08:08:00.000+05:302018-12-23T01:21:44.206+05:30How to fix min pulse width violationIn our previous posts, we discussed about the duty cycle, duty cycle variation and duty cycle degradation. Bad duty cycle impacts half cycle timing paths and has impact in meeting timing for minimum pulse width checks of flip-flops. However, there are certain techniques available that can help you in improving the duty cycle of the clock. We will discuss these techniques in this post as below:1. adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-11600338073298749982017-10-17T10:25:00.000+05:302018-12-23T01:21:44.504+05:30Duty cycle degradationIn the post, we discussed about duty cycle variation of the clock source. However, this is not the only pain in half cycle timing paths. Along clock path also, duty cycle of the clock can degrade. This can effect timing of half cycle paths adversely. We will discuss this in some detail; and also discuss how to tackle this. How is there degradation in duty cycle of clock: In addition to adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-30969249798194225042017-10-08T19:39:00.000+05:302018-12-23T01:21:44.799+05:30Computer bug!!adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com1tag:blogger.com,1999:blog-1138057977667010432.post-89735364866031395232017-10-02T19:56:00.000+05:302018-12-23T01:21:45.137+05:30Logic design interview questionsBCD multiply by five circuit2-bit binary multiplierImplement 3 and 4 variable functions using 8:1 mux16x1 mux using 4x1 muxesDelay line based time-to-digital converterHow to build an XOR gate with NAND gatesMultiply by 2 clock circuitImplement 3-input gates using 2x1 muxesDivide by 2 clock in VHDL3-input AND gate using 4:1 mux2x1 mux using NAND gatesXNOR gate using NAND8x1 multiplexer using 4x1 adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-35843116891795565592017-10-02T12:35:00.001+05:302018-12-23T01:21:45.679+05:30Duty cycle variationDuty cycle variation: Similar to jitter in clock period, there can be variations in duty cycle of the clock source due to uncertainty in the relative timings of positive and negative edges. Duty cycle variation is always measured with respect to corresponding positive and negative edges. In other words, we can also say that duty cycle variation is the uncertainty in arrival of negative edge, adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-6274680793497412082017-10-02T12:35:00.000+05:302018-12-23T01:21:45.434+05:30Duty cycle variation of inter-clock timing pathsIn the post, duty cycle variation, we understood what duty cycle variation is, and how to apply for intra-clock timing paths. But of similar importance is duty cycle variation as applied to inter-clock timing paths. Let us discuss these cases one-by-one:Root clock to root-inverted clock: Inverted clock is same as root clock in frequency, with phase inverted. So, duty cycle variation needs to be adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-80127709940983480332017-09-03T21:15:00.000+05:302018-12-23T01:21:45.927+05:30Duty cycle of clockDuty cycle: Duty cycle of a clock is defined as the fraction of a period of clock during which the clock is in active state. Duty cycle of a clock is normally expressed as a percentage. For instance, figure below shows a clock having an active state of '1' stays low for 2 ns during its period of 10 ns. It is, therefore, said to have a duty cycle of 20%.How duty cycle impacts timing: Duty cycle&adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-88017549108834901752017-08-28T21:03:00.000+05:302018-12-23T01:21:46.222+05:30Which type of jitter matters for timing slack calculation?In the post Clock jitter, we learnt about the basics of clock jitter. We also learned about different types of clock jitter. Now, the question arises as to what type of clock jitter is useful for calculation of timing slack, both setup and hold slacks. We will gradually try to build understanding for the same. If we look into the equation of setup slack for a positive edge-triggered flip-flop to&adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0tag:blogger.com,1999:blog-1138057977667010432.post-74997391025040042632017-08-21T21:43:00.000+05:302018-12-23T01:21:46.516+05:30Clock jitterClock jitter: By definition, clock jitter is the deviation of a clock edge from its ideal position in time. Simply speaking, it is the inability of a clock source to produce a clock with clean edges. As the clock edge can arrive within a range, the difference between two successive clock edges will determine the instantaneous period for that cycle. So, clock jitter is of importance while talking adminhttp://www.blogger.com/profile/12886553984280308121noreply@blogger.com0